00:00Hello everyone.
00:01Welcome to our FPGA design course with VSGL.
00:05In this video we will give you little brief about what we are going to cover in this learning
00:10series.
00:11By the end of this course you will be able to design your complex FPGA projects with
00:15confidence using VSGL.
00:17So let's dive in and start mastering this language together.
00:21Throughout this course we will work on the variety of projects and practical exercises
00:25to develop the deep understanding of VSGL and FPGA.
00:29We will begin with the straightforward projects and then gradually increase the complexity
00:34of our projects to design bigger systems.
00:37To test these projects we will use the cyclone 2 development boot for the experiment with
00:42the real hardware.
00:44In this course we will cover the essential topics such as signals, constraints, generics, variables
00:49and many many more things.
00:51These are fundamental concepts that form the basic building blocks of VSGL.
00:55We will explore the various data types in VSGL and learn how to create the custom data types
01:01as well.
01:03Additionally, we will go into the type conversions.
01:06This feature will enable us to convert the data between different data types.
01:11We will use the typecasting functions and VSGL functions to convert between different data
01:15types.
01:17After that we will learn about the VSGL operators.
01:20There are around 30 VSGL operators and we will cover each one in details later.
01:26Next we will explore the process and block statements in VSGL.
01:30We will cover both the registered version and the combinational version of these statements
01:35including the sensitivity list.
01:37You will learn that how to determine which signals should include in the sensitivity list.
01:42We will also discuss the general structure of the VSGL files.
01:47We will cover the entity declaration, the architecture declaration and the overall structure of
01:52VSGL files.
01:53Additionally, we will learn how to instantiate components and create the structural designs.
02:00We will discuss nearly all the VSGL keywords including both concurrent and sequential statements.
02:05Lastly, we will explore the functions and procedures which are useful for performing the actions
02:12that need to be repeated multiple times.
02:15We will also explore the VSGL libraries and packages, both existing ones and how to create
02:21your own.
02:22Throughout this course we will use the numerous examples to demonstrate how to apply VSGL concepts
02:28in various scenarios.
02:31These examples will demonstrate the use of specific keywords and the options available when
02:35we are using them.
02:37Next we will be creating the full designs including finite state machines, shift registers, serializers,
02:44memory components such as RAM, ROMs, etc., multiplexers, tri-state drivers, comparators, etc.
02:51We will walk through these examples step by step.
02:54Additionally we will talk about several FPGA projects that we will implement and load onto the
02:59FPGA development board.
03:02This hands-on approach allows us to test our code in real hardware and interact with it
03:06to ensure that our FPGA design functions as expected.
03:11Our first project will involve creating the input from a single switch and controlling a
03:16single LED output.
03:18This project is focused on understanding the tools and procedures required to implement a
03:23project and program the FPGA on board.
03:26Next we will implement a simple state machine on the FPGA development board.
03:31This example will demonstrate that how the state machines can be implemented and run on
03:36the real hardware.
03:38Next we will tackle a slightly more complex topic which is how to synchronize the asynchronous
03:43input.
03:44We will focus on debouncing a switch input and discuss the approach how to achieve this.
03:50We will explore that how to generate a PWM pulse width modulation signal using an FPGA.
03:57We will cover a simple method for generating pulses including how to vary the period and
04:02adjust the duty cycle of it.
04:06Next we will dive into designing a shift register on the FPGA development board.
04:11This topic adds a bit more complexity to our project.
04:14We will develop a 4 digit 7 segment display on the board to show a number that corresponds
04:19that how many times the switch has been pressed.
04:23This project adds a practical aspect by interacting with the ports and its components.
04:29And it will add a hands-on element to our learning experiences.
04:32Lastly, we will develop a communication module, a UART universal asynchronous receiver transmitter
04:39module.
04:41This module will work alongside the state machine and enable the communication between the FPGA
04:45development board and a computer over the RS-232 interface.
04:49We will make the extensive use of Intel Quartus software in this course.
04:55We will use it to create and compile our FPGA projects as well as performing the pin assignments.
05:02Pin assignment is the tool which involves mapping ports in a VSDL file to the physical pin on
05:07the FPGA device itself.
05:10Pin assignment is the process of mapping ports in our VSDL code to the physical pin of the
05:16FPGA device.
05:18This step is crucial for ensuring that our designs functions correctly on the actual hardware.
05:25I will walk you through how to perform this in this course.
05:28I will also give you a basic understanding of how to use the Quartus IP catalog.
05:34This catalog contains pre-designed VSDL components that you can select, drag and drop into your
05:40VSDL project.
05:41This feature simplifies the designer's life because most of the work has already been
05:46done in these catalogues.
05:48All you need to do is just learn how to generate these IP designs and then incorporate them into
05:53your own projects.
05:55I will provide an example to show you how to use Quartus IP catalog in this learning series.
06:01Additionally, I will demonstrate how to use the USB plaster to program the FPGA.
06:08This is particularly useful for testing purpose right after compiling your projects on the
06:12development board.
06:13We will also explore some of the output reports of the Quartus packages including the netlist
06:20viewer.
06:21This tool is quite useful because it allows you to see the hardware realization in your
06:26design.
06:27When you write your VSDL code, it exists in the text editor, however on the physical device
06:33it is implemented using the registers, combination logic and gates such as AND gate, OR gate, NOT
06:39gate etc.
06:40And all these things are connected by some wiring, right?
06:44The netlist viewer provides a visual representation of this hardware realization, helping you to
06:49understand how the physical hardware performs the functions which you are describing into the
06:54VSDL.
06:55We will also explore the fitter reports which is another type of report provided by Quartus.
07:02This report is valuable for understanding the resource consumed by your VSDL design.
07:07It provides the detailed information about the allocation of the resources on the FPGA
07:12and giving you the insights into how efficiently your design is using the available hardware.
07:18You will be able to see that how many registers and gates your design uses among all other things.
07:25This report gives you a comprehensive overview of the resource usage and help you identify
07:29where the resources are being utilized.
07:32We will also explore the Quartus assignment editor.
07:36This tool allows you to fine-tune the implementation of your design.
07:40While your VSDL code describes the behavior of your design, the assignment editor helps you
07:46to optimize how that code is translated into the physical hardware by the Quartus compilation
07:52process.
07:53We will also explore the other settings, options and optimizations available within the Quartus.
08:00Additionally, I will provide a basic introduction on the timing analyzer and how to create a basic
08:06timing constraints including generating an SDC file.
08:10However, this coverage will be introductory.
08:14For verification and simulation, we will be using ModelSim.
08:17I will demonstrate that how to create and compile ModelSim projects, write module label and system
08:24label testbench models and use text files to generate inputs and output vectors for testing.
08:31By using the assignment editor, you can influence how specific sections of your code or design
08:36are implemented in the hardware.
08:39This optimization can lead to better overall design efficiency.
08:44Understanding how to test a complex RPG design is very crucial.
08:47We will cover that how to perform the simulations using ModelSim, including developing the comprehensive
08:54test benches especially for the final project.
08:57We will write the test benches at the module label for the various modules and ultimately
09:04design a system label test bench to ensure the entire system functions correctly when all
09:09the modules and all the modules are integrated.
09:12We will use the wave window in ModelSim to analyze our results and ensure that they are aligned with
09:18our expectations.
09:20This approach ensures that our FPGA designs are thoroughly tested and functions as intended.
09:26This FPGA development board with the Cyclone 2 device looks great.
09:30It has 7 segment display which will definitely come in handy for our projects.
09:35It seems like a very capable board for learning and experimenting with FPGA design in budget.
09:42You can also try the mid-range FPGA devices as well like Cyclone 4 devices etc.
09:48The other thing that is highly useful about this development board is that it has these
09:53header pins.
09:54These general purpose input-output headers on the board let you easily connect other hardware
10:00on the FPGA for experiments.
10:03This flexibility is great for trying our new ideas.
10:07This is quite useful if you want to experiment by plugging in other hardware modules onto your
10:12FPGA development board.
10:13There are also an LCD connector at the side which means you can connect and control an external
10:20LCD device with this FPGA.
10:24This summarizes what we will cover in this course giving you a good understanding of FPGA
10:29designs.
10:30Hope you are looking forward to it.
10:32In the next session I will show you the easiest way to grab the Quartus Prime software for free
10:37to practice the exercises of this course.
10:40So stay tuned for the updates.
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