8 - এক ভিডিওতে সকল লজিক সার্কিট AND gate OR gate NOT gate HSC DSD(1) - video Dailymotion

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Transcript

00:00logic gate

00:07now we will have a topic of logic gate

00:11logic gate is a different way

00:16fundamental logic gate

00:19and composite logic gate

00:21fundamental logic gate

00:25but mainly logic gate

00:27and gate

00:28or gate

00:29or not gate

00:32and or not gate

00:34I am going to combine

00:36composite logic gate

00:37here we go

00:39nan gate

00:40nor gate

00:41xor gate

00:42xnor gate

00:43and or not gate

00:45or not gate

00:48or not gate

00:49or not gate

00:51then

00:52exclusive or gate

00:54exclusive not gate

00:56so mainly

00:57these three gate gate

00:58number

00:59key ideas

01:00in this gate

01:01we will have to go

01:02to this gate

01:03and we will have to go

01:04to this gate

01:05and we will have to go

01:06to this gate

01:07logic gate

01:08data value

01:09in this gate

01:10positive logic gate

01:12logic gate

01:13logic gate

01:154.85 volt

01:18high volt

01:19logic

01:20LOGIC 2

01:220.4

01:231 volt

01:240

01:24low volt

01:25negative

01:27logic gate

01:288

01:29logic 1

01:300.4

01:311 volt

01:32logic 2

01:33suppose

01:344.8

01:355 volt

01:36we have the

01:37high

01:38true

01:39connection

01:411

01:42because

01:43high

01:44true

01:451

01:46simple

01:471

01:48A low, false, off, and 0 is the system of a connection of a signal of a signal of a signal of a signal.

01:59In a logic gate, some digital signal enters in a circuit and one digital signal out from it.

02:09In a logic gate, some digital signal input, then calculation, then a signal output.

02:19If we see the AND gate, the AND gate is defined by A.

02:28The first thing we can see is that F is F, and F is F.

02:38The first thing we can see is F.

02:40We can see F.

02:42We can define F as F as F.

02:46We can see F as F as F.

02:48The first thing we can see is that DUT signal is 1.

02:51The second thing is DUT signal is 1.

02:53Then the second thing is 1.

02:55The first thing is B is true.

02:56It may Н stash q actually becomes 0, but the next thing is false, is false.

03:01For this S and ag signal you have signal.

03:04This both signal means 1.

03:05X and Y into the details.

03:08This way that the output is F is input by its output.

03:11This is Y input, then the X output.

03:14As you have alpha strings valid, then the end symbol is written.

03:19This is limits on AND Toot 2 components.

03:22F1 x y 0 x 1 x 0 x 1 x 0 xART

03:29F1 x 0-1 x 0-to-1 x 0-to-1 x2 x 0 x 0-to-1 hatefuls

03:31hatefuls hatefuls 우 malts

03:34Akta false, true of false

03:39raise162 is co2 x 2-0

03:41beliefs F1 oooq

03:43줄ers sería hijab 672 false

03:47between 2 and double actions

03:49we will see Big C Jake

03:51signal is 1. Then we can say this signal is 1.

03:58We can add 0, 1, 0, 1 because

04:02we have one variable.

04:05We have two options for each portion.

04:08We can add that option.

04:10We can add 0, 1, 0, 1.

04:13We can add 0, 1, 0, 1.

04:15We can add 0, 1, 0, 1.

04:18We can add 0, 1, 0, 1, 0, 1.

04:22We can add 0, 0, 0, 1.

04:24Then we have 4, 0, 4, 1.

04:27We can add normal parts that we have zero to the number 1,

04:31so the number 1 will be zero to the number 1,

04:32and this will be zero I, one representation.

04:34Then we can add 0 to the number 1,

04:38and we can add 1 to the number 1.

04:41Now, if we add 0 to the number 1,

04:43we will add 0 to the number 1,

04:44ON, once we have zero,

04:47Watch the e3 connection to this e3 connection

05:09котор u bari out hu ba, ba yi khane mularak ca bari jay actor true ho le output true ho wabay

05:17out that jehkun ekti signal on tha ki li ho en, yi khane dueyte signal on tha ki

05:24har dor ka naay, yi khane just ekti signal on tha ki li output on ho wabay.

05:28tada output output saipta ho ba light on tha ki bo or ki te symbol ho do thik ee rokhun

05:38So we have a x, a x will act the input, y will act the input, and output is f.

05:45Then a x, y will act the truth, 0, 1, 0, 1, data 0, data 1.

05:52Then 0, 0, data signal is off.

05:56Then act the signal is off.

05:59Then the output is out.

06:02Then the output is out.

06:04Then act a 0, act a 1, then the output is 1.

06:08This is act a 1, act a 0, output is 1.

06:12Act a 1, act a 1, again the output is 1.

06:16So we have the main theme that we have at war gate for main theme.

06:22Then we have the first input.

06:24Now the input 가운데 1 is 1.

06:28Now we have the output as a switch 1.

06:31and the light LED bulb is installed

06:39not get

06:41not get is inverse

06:43when not get is 2.0

06:47not get

06:49not get

06:51not sign

06:53buffer get

06:55not sign

06:57add

06:59not get

07:01not get

07:09not get

07:11not get

07:13not get

07:15not get

07:17good

07:19.

07:21signal which we have output and input which we have signal which we have output

07:28n-get

07:32if we have not-get plus n-get we have n-get

07:38we have n-get

07:42we have n-get

07:51we have n-get and not-get

07:57we have not-get

08:01then we have n-get

08:03we have n-get

08:06we have x-get input

08:09y-get input

08:11and output

08:13xy

08:15y-get 0-get

08:17we have n-get

08:19xy

08:23xy

08:25xy

08:27c

08:30xy

08:320

08:34xy

08:36xy

08:39xy

08:41xy

08:44xy

08:46xy

08:47inverse n get inverse n get 0 and 0

08:53n get 0 is false

08:560 is inverse 1

09:00n get inverse n get inverse

09:03n get 0 is 0 and n get 1

09:061 is false then 0 is 0

09:09but n get 1

09:12n get 0 is 0

09:16n get is 1

09:19n get is inverse

09:21n get at backwards

09:23inverse

09:24n get is 0

09:26n get is 0

09:28n get is 0

09:30n get is 0

09:32jane

09:34n get

09:37n get is 0

09:40as well so it alone and get a truth table nor get or get a sadd me not get at

09:49kori then number problem or get a nor get or take or get it in bars that the

09:55camera ever denote cut to bari ever denote cut to bari txyz did a input high it

10:03or get or get a sadd mek not get at column so overall my nor get hello nor get

10:08answer has be tk e roko nor get truth table to a juri dekhi xy truth table

10:15I mean 0 1 0 1 do it 0 1 do it 1 do it 1 do it 1 do it 1 do it 1 do it 1 do it 1 do it

10:24so here it is false so output is false because here it is nor get

10:30kurtulate universe that 1 do it 1 do 8 do it 1 do it 1 do that 1 do 10 do it 1 do it 1 do it 1 do it 1 do it 2 do it 1 do it 4 do word

10:42shock have an idea but know or get 1 do it 1 do it 2 do it 1 do it 1 do it 1 do NOT get 1 do it 1 do ого their

10:52and we will be able to do it.

10:58Exargate

11:00Exargate is exclusive overgate

11:04Individually

11:06just active input

11:08signal

11:09circuit open

11:10otherwise

11:11circuit open

11:12individually

11:14individually

11:16active input

11:17signal

11:18circuit open

11:19otherwise

11:20due to

11:22due to

11:23due to

11:24signal

11:25due to

11:26due to input

11:27signal

11:28circuit

11:29open

11:30circuit open

11:31circuit open

11:33here

11:34here is the

11:36OR gate

11:37OR gate

11:38sign

11:39and

11:40here is the

11:41sign

11:42which

11:43is

11:44exargate

11:45exclusive

11:46OR gate

11:47A

11:48B

11:49due to input

11:50or

11:51output

11:52OR gate

11:53exclusive

11:54OR gate

11:55A

11:56OR

11:57B

11:58and

11:59sign the tag

12:00exclusive

12:01OR

12:02ve

12:09input

12:100

12:111

12:120

12:130

12:140

12:150

12:160

12:170

12:181

12:190

12:200

12:210

12:220

12:230

12:24individually just active input

12:28which is the signal

12:32active input signal on

12:36active input signal on

12:40circuit off

12:42active input signal

12:44active input signal

12:46circuit on

12:48say here

12:50after the circuit

12:52and there

12:54carrying the two

12:55connected

12:56and there

12:57that means

12:59whenever

13:01these

13:02�잖

13:04типа

13:06the�

13:08department

13:10i

13:12we

13:14saw

13:15але मैं भीभावन मा गूका तवयदी बीजकों गशंका के निप Woo

13:19आपूद ठ्रू होए वीजकों का इंपुजी ट्रू हाए proto

13:23आप निपर एक्ट्रू बचियों का एक्टों क आप्टक्वा अहिक ā घृत्र रै

13:29आपра ő था Ball

13:31the output is not true and the output is not true

13:37the exclusive nor is the exclusive nor is the

13:43exclusive nor is the x or the inverse

13:47the inverse is the inverse

13:49the difference between duty is the same input

13:53the output is true

13:55the output is same way then token

13:57output is true

14:05x or inverse is not

14:07x not

14:09x or symbol

14:11x or symbol

14:13x not

14:15x not

14:17x not

14:19x not

14:21x not

14:23x not

14:25everything is the

14:33x not

14:35x not

14:37x not

14:39x not

14:41x not

14:43x not

14:45x not

14:47y not

14:49x not

14:51Same. So, output true.

14:53Here is the input 0 and the input 1.

14:57Here is the input same.

14:59The output is out.

15:01Output 0.

15:03But output false.

15:05Here is the input on and the input off.

15:10So, output is the output.

15:13But here is the input on and B input on.

15:16The input on is on.

15:18The input is same.

15:20So the output is true.

15:23And what I want to say is BufferGet.

15:26BufferGet symbol is simple.

15:29If you go to input and output,

15:32then the output is true.

15:35BufferGet opposite is not get.

15:38BufferGet normally is not done,

15:41but logic is wrong.

8 - এক ভিডিওতে সকল লজিক সার্কিট AND gate OR gate NOT gate HSC DSD(1)

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