Séminaire LRDE - Platform and Research overview on the Intel Single-Chip Cloud Computer - Roy Bakker http://seminaire.lrde.epita.fr/2012-10-17.php
The Single-chip Cloud Computer (SCC) is a 48-core experimental processor created by Intel Labs targeting the many-core research community. The 6x4 mesh Network-on-Chip provides 24 tiles with 2 cores each. All cores are independent and run their own instance of an operating system. It has hardware support (local buffers on the tiles) for sending short messages between cores, and allows for voltage and frequency control at 8 and 2 cores respectively. We have already modified the SVP runtime system to use these on-chip buffers for the communication between threads executed on separate cores. We also created a visual application for manual process migration and scheduling on the SCC as well as a library for customized voltage and frequency scaling on the chip. Currently we focus on automated parallelization and mapping of one or multiple sequential programs onto the 48 cores by modifying the daedalus framework to target the SCC. The daedalus framework parallelizes sequential C programs using Kahn Process Networks (KPNs) and generates code to run the KPN on multiple hardware platforms like for example an FPGA, SMP CPU or GPU. The SCC backend, which is work in progress, should result in a tool that utilizes the SCC cores in an optimal way by means of performance and energy consumption. It should also allow the system to dynamically adapt on changes in the computational or communicational needs of the processes by scaling frequency and migrating processes.